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2018年度盛会NCAP&Yole先进封装及系统集成专题研讨会新鲜发布!

       

       华进半导体暨半导体封装技术研究所,与法国著名市场调研公司Yole共同组织的先进封装及系统集成专题研讨会将于2018年6月20日-21日在无锡日航酒店举办,Yole将与大家分享行业趋势,并邀请先进封装领域的关键企业参与专题讨论。本次先进封装及系统集成专题研讨会,内容覆盖封装5大方向,包括:板级封装、Fanout、系统级封装、先进基板、以及3D封装技术等等。会议将重点关注目前炙手可热的应用,如5G、AI、汽车及存储。

       同往届相比,本次新增半天短训班,特邀汪正平院士、日月光集团工程副总郭一凡博士和中科大林福江教授为大家分别作电子封装技术及材料、高性能计算和先进封装技术开发及射频IC设计封装表征与建模的报告。

       请关注华进微信公众号或官网(www.ncap-cn.com)获取最新信息。

       会议日期    2018年6月20日-6月21日
       会议地点    无锡日航酒店3楼永乐厅(无锡梁溪区永乐东路9号(向阳路与永乐东路交叉口))
       注册平台    https://www.eiseverywhere.com/ereg/index.php?eventid=332224& 

       活动亮点    

       1.    聚集国内外封装行业知名企业及院校(工艺/材料/装备);
       2.    性价比超高的半天短训班
       3.    20位行业大拿分享前沿技术及市场动态
       4.    内容新颖、覆盖面广:5大封装方向,4大热门应用
       5.    鸡尾酒派对提供高价值的社交机会

       咨询电话    0510-66679351
       咨询信箱    Xiaoyunzhang@ncap-cn.com(NCAP);veyrier@yole.fr (Yole)
       会议网站    NCAP&YoleSymposium

       自研讨会发布以来,受到国内外行业同仁的广泛关注。在华进和Yole的共同努力下,出席2018年研讨会的演讲嘉宾名单及演讲内容已基本确定。

Short Courses Session/短训班(620日上午)

1

电子封装技术及材料

CP Wong, GaTech

2

高性能计算和先进封装技术开发

YifanGuo, VP of Engineering, ASE Group

3

射频集成电路设计的精确封装表征与建模

Fujiang Lin, Professor, University of Science & Technology of China

Symposium/研讨会(620日下午-621日)

1

Keynote行业趋势对先进封装的影响

Jean-Christophe Eloy, President & CEO, Yole Développement

Session: Panel Level Packaging/板级封装

2

MOSFET嵌入式基板

Sky Ran, Key Account Manager, Schweizer Electronic (Suzhou)

3

MultiPlate®:新一代功率半导体电镀设备

Yen Ho Chen, Business Manager, Atotech

4

拥有卓越均匀性的板级先进封装电镀

Raoul Schroeder, Head of Product Management, Semsysco

5

从晶圆级到板级量产的低成本溅射方案

Andreas Erhart, Senior Manager, Product Marketing Advanced Packaging, Evatec

Session: High End/高端

6

16/14nm芯片晶圆级三维集成研究进展

Dr. Wenhui Zhu, Professor, Central South University

7

先进封装设备及工艺的挑战

Laura Mauer, Chief Technical Officer, Veeco

8

适用于高频IC芯片测试的阻抗控制结构

Jiachun Zhou (Frank), Smiths Interconnect

Session: Fan-Out WLP/晶圆级扇出封装

9

硅基扇出型封装技术的产业化之路:eSiFO®

Dr. Daquan Yu, Vice President, Huatian Technology (Kunshan) Electronic

10

华进晶圆扇出型封装的进展

Daping Yao, Ph.D., Technical Director, NCAP China

11

高密度封装时代的晶圆扇出型加工

David Butler, EVP General Manager, SPTS Technologies

12

热拆键合和翘曲校准的十年历程

KlemensReitinger, CEO, ERS electronic

13

针对高密度晶圆扇出型封装中细线宽线距RDL层的缺陷检查

Stephen Hiebert, Senior Director of Marketing, KLA-Tencor

Session: Equipment for WLP/晶圆级封装装备

14

针对Wafer-On-Frame的等离子清洗方案

Jack Zhao, Ph.D., Chief Scientist/Applications Director, Nordson March

15

先进封装载板拿持技术

DongshunBai, Ph.D., Deputy Business Development Director, Brewer Science

16

先进晶圆键合技术

Dr. Thomas Uhrmann, Head of Business Development, EV Group 

17

未来新趋势:柔性混合电子带来行业革新

Chong Chan Pin, Senior Vice President, EA/APMR and Wedge Bonders Business Lines, Kulicke&Soffa

Session: Advanced Packaging Materials/先进封装材料

18

针对bumping工艺的Dipsol TS-3500(SnAg)化学药液解决方案

Atsushi Sakamoto, Manager, Dipsol Chemical

19

德邦翌骅的产品现状及未来研发方向

MinghuaLuo, General Manager, DongguangDarbondYizTech Material


       注:除短训班以外,研讨会演讲内容及顺序请以最终发布的活动议程为准。

       附:短训班讲师介绍及讲座摘要

       1.    Electronic Packaging Technology and Materials

       Abstract:Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel No Flow Underfills, ReworkableUnderfills for Ball Grid Array (BGA), Chip Scale Packaging (CSP), System in a Package (SIP), Direct Chip Attach (DCA), Flip-Chip (FC), Paper-thin IC and 3D Packaging, Conductive Adhesives (both ICA and ACA), Embedded Passives (high K polymer composites), nano particles and nanofunctional materials such as CNTs, graphenes. It is imperative that both material suppliers, formulators and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies.

       About the speaker:Prof. Wong is a Regents’ Professor and the Charles Smithgall Institute Endowed Chair at the School of Materials Science and Engineering, Georgia Institute of Technology (GT) and is the Dean of the Faculty of Engineering School, City University of Hong Kong (CUHK). He is also the team leader of the Guangdong Innovation Team for the Advanced Electronic Packaging Materials (SIAT). Professor Wong has published widely with over 1000 technical papers and yielded fruitful research results and holds over 50 US patents. Professor Wong is considered an industry legend and has made significant contributions to the industry by pioneering new materials, which fundamentally changed the semiconductor packaging technology.

       Professor Wong was awarded numerous international honors, such as being elected as AT&T Bell Laboratories Fellow in 1992, the IEEE CPMT Society Outstanding Sustained Technical Contributions Award in 1995, member of the US National Academy of Engineering in 2000, the IEEE Third Millennium Medal in 2000, the IEEE EAB Education Award in 2001, the IEEE CPMT Society Exceptional Technical Contributions Award in 2002, the Georgia Tech Class 1934 Distinguished Professor Award in 2004, named holder of the Charles Smithgall Chair (one of the two GT Institute Chairs) in 2005, the GT Outstanding PhD Thesis Advisor Award, the IEEE Components, Packaging and Manufacturing Technology Field Award in 2006, the Sigma Xi’s MonieFerst Award in 2007, the Society of Manufacturing Engineers’ Total Excellence in Electronic Manufacturing Award in 2008 and the IEEE CPMT David Feldman Award in 2009 and Dresden Barkhausen Award in 2012. He has recently received the Pennsylvania State University Outstanding Science Alumni Award.

       2.    HPC and Advanced Packaging Technology Development

       Abstract: In recent development of semiconductor technologies, it is becoming more and more clear that the AI, typically presented by the cloud computations, autonomous vehicles and neural networks, will be the next major area of applications.  One of the key characteristics of the AI applications is that it demands for high speed and extensive computation power.  However, since the Moore’s Law is approaching its limit and the IC performance improvement by scaling will slow down eventually, using packaging technology to enhance the IC performance becomes urgent and important. In this presentation, the evolution of packaging technologies in high speed applications is introduces. Several advanced packaging platforms and their design and process challenges are presented. New and potential packaging solutions and development progress are discussed.

       About the speaker: YifanGuo is a Vice President of Engineering in ASE Group.  In past 30 years, he has taken positions as Professors and Adjunct Professors at Virginia Tech, State University of New York at Binghamton and University of California at Irvine. He has also worked for IBM, Motorola, Skyworks, ASE, and held positions from middle to high level management in charges of R/D, engineering and operation. He has published 7 book chapters, 9 patents and more than 50 refereed journal papers. YifanGuo got his Ph.D degree from Engineering Science and Mechanics (ESM) Department at Virginia Tech. and MBA degree from School of Business at University of Redlands in California.

       3.    Accurate Package Characterization and Modeling for RFIC Design

       Abstract: Packages have great impacts on RFIC and high-speed IC performance for both bond-wire and package lead. They should be accurately characterized and modeled preferably in an equivalent circuit (EQC) model, so that they can be co-simulated for a reliable RFIC design. Although EM simulation is now widely used, it should be verified by practical measurement. This lecture will talk about experimental technique for accurate package modeling including full L and C matrix, as well as ground inductance based on VNA technique using RF probe station. Advanced EQC models are developed for RFIC design which have been proven for first-pass succss in packaged IC testing.

       About the speaker: Fujiang Lin received the BSEE and MSEE degrees from USTC, Hefei, China, and the Dr.-Ing. degree in MMIC from the University of Kassel, Germany. Dr. Lin has been the “Chinese K-Talent Program” full time professor at USTC since 2010. He established the USTC Micro/nano-Elecronic System Integration R&D Center (MESIC) focusing on advanced nanotech devices modeling and IC design.Prior returning back USTC, Dr. Lin worked as SMTS and PI in the Institute of Microelectronics, A*STAR, Singapore; as adjunct Associate Professor at NUS; as Director in CHRT (now GlobalFoundries), as Technical Director at HP/Agilent (now Keysight) EEsof; as founder and CEO of Transilica Singapore.Professor Lin has extensive hand-on and multi-discipline experiences and knowledge in advanced micro-/nano-electronics technologies, RF modeling for MMIC/RFIC and Packages, as well as the related integrated circuits and system design.

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